1. Field of the Invention
The present invention relates to internal clock signal generation circuits, and more particularly to a circuit and method that can produce an internal clock signal correctly in synchronization with an external clock signal.
2. Description of Related Art
When a system with a semiconductor memory device is operated at high speed, it is important to take into account a skew between a clock signal that the semiconductor memory device externally receives and data output from the semiconductor memory device, in order to correctly transfer the data output from the semiconductor memory device to an external processing device.
Typically, the semiconductor memory device includes an internal clock generation circuit to generate an internal clock signal in synchronization with an external clock signal, thereby minimizing the skew. The internal clock generation circuit typically includes a phase-locked loop circuit and a delay-locked loop circuit.
Unfortunately, the phase-locked loop circuit requires several hundred clock signals; and the delay-locked loop circuit is serially connected to a plurality of unit delay circuits comprising each of a pair of inverters, resulting in increased layout area and complexity of the circuit.
An advantage of the present invention is to provide a circuit and method that can produce an internal clock signal correctly in synchronization with an external clock signal without using a plurality of unit delay circuits, thereby simplifying the structure of the circuit.
To achieve this advantage of the present invention, an internal clock signal generation circuit comprises a first delay means for delaying an external clock signal by a first delay time; a divider for dividing an output signal from the first delay means; a first signal generation means for producing a first signal with a pulse width equivalent to a skew monitor time, by delaying an output signal from the divider by a second delay time (e.g., the first delay time+a third delay time+a fourth delay time) and by combining the output signal from the divider with a signal delayed by the second delay time; a second signal generation means for producing a second signal with a pulse width equivalent to the third delay time at a falling (or rising) edge of the output signal from the first delay means; a time/digital signal converter means for converting the skew monitor time equivalent to the pulse width of the first signal into a first and a second digital signals in response to the first signal; and a digital signal/time converter means for reproducing the skew monitor time by inputting the first and second digital signals in response to the second signal, and outputting an internal clock signal being delayed by the fourth delay time from the skew monitor time reproduced.
Furthermore, the time/digital signal converter comprises a first ring oscillator for generating in response to the first signal n number of first pulse signals, the first ring oscillator including n number of first inverting circuits serially connected; a transmitter for outputting in response to a falling (or rising) edge of the first signal the n number of the first pulse signals; a phase detector for detecting phases of the n number of the first pulse signals to produce the first digital signal; and a first counter for counting in response to a falling (or rising) edge of a nth pulse signal of the n number of the first pulse signals to produce the second digital signal.
The digital signal/time converter comprises a set/reset signal generation means that produces a set signal, if the first digital signal is at an even state, and produces a reset signal, if the first digital signal is at an odd state; a second ring oscillator for generating in response to the second signal and the set signal n number of second pulse signals being oscillated with a first type, and for generating in response to the second signal and the reset signal the n number of the second pulse signals being oscillated with a second type, the second ring oscillator including n number of second inverting circuits connected in series; a select control signal generation means for producing n number of control signals to output selectively a corresponding pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting rising (or falling) edges of a 1st pulse signal to the nth pulse signal of the first pulse signals, and output selectively a (corresponding order+1)th pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting falling (or rising) edges of the 1st pulse signal to the nth pulse signal of the first pulse signals; a selection means for selecting one pulse signal of the n number of the second pulse signals output from the second ring oscillator in response to the n number of the control signals; a second counter for counting in response to an output signal from the selection means; and a comparison means for comparing an output signal of the first counter with an output signal of the second counter, and delaying and outputting the output signal of the selection means by the fourth delay time, if the output signal of the first counter is equal to the output signal of the second counter.
To achieve a further advantage of the present invention, a method for generating an internal clock signal comprises generating a first clock signal by delaying an external clock signal by a first delay time; generating a second clock signal by dividing the first clock signal; generating a third clock signal by delaying the second clock signal by a second delay time (the first delay time+a third delay time+a fourth delay time), and generating a first signal with a pulse width equivalent to a skew monitor time in combination with the second clock signal and the third clock signal; generating a second signal with a pulse width equivalent to the third delay time at a falling (or rising) edge of the first clock signal; converting the skew monitor time equivalent to the pulse width of the first signal into a first and a second a digital signals in response to the first signal; and reproducing the skew monitor time by inputting the first and the second digital signals in response to the second signal, and generating the internal clock signal being delayed by the fourth delay time from the skew monitor time reproduced.
Preferably, the time/digital signal converting comprises generating n number of first pulse signals being oscillated in response to the first signal; outputting the n number of the first pulse signals in response to a falling (or rising) edge of the first signal; and detecting phases of the n number of the first pulse signals to produce the first digital signal, and counting in response to a falling (or rising) edge of a nth pulse signal of the n number of the first pulse signals to produce the second digital signal.
Preferably, the digital signal/time converting comprises producing a set signal, if the first digital signal is at an even state, and producing a reset signal, if the first digital signal is at an odd state; outputting selectively a corresponding pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting rising (falling) edges from a 1st pulse signal to the nth pulse signal of the first pulse signals, and outputting selectively a (corresponding number+1)th pulse signal of the second pulse signals for the case where the first digital signal is produced by detecting falling (or rising) edges from the 1st pulse signal to the nth pulse signal of the first pulse signals; generating n number of the second pulse signals being oscillated with a first type in response to the second signal and the set signal, and generating the n number of the second pulse signals being oscillated with a second type in response to the second signal and the reset signal; selecting one pulse signal of the n number of the second pulse signals in response to n number of control signals to output a selected output signal; counting in response to the selected output signal to produce a third digital signal; and comparing the second digital signal with the third digital signal, and delaying and outputting the selected output signal by the fourth delay time, if the second digital signal is equal to the third digital signal.
Other aspects, features and advantages of the present invention are disclosed in the detailed description that follows.